1. Field of the Invention
The present invention relates to, but is not limited to, electronic devices, and in particular, to the field of clock circuits.
2. Description of Related Art
Clock signals are basic elements in digital circuits. A clock signal, generated by a clock generator, may be used to trigger flip-flops, serve as a timing reference, provide data and address strobing, and perform many other timing and control functions. To distribute the clock signal to various circuit elements, a clock distribution circuit is used.
The clock pulse signal has a frequency and a duty cycle. The duty cycle is defined as the ratio between the high period over the entire period of the signal. The ideal duty cycle for a clock signal is 50%. The reason clocks become unbalanced, drifting away from the 50% duty cycle, is that a digital logic element may have an asymmetric response to rising and falling waveforms, so that the propagation delay for the logic element differs for rising and falling clock edges. The clock signal propagating through the logic element is either shortened or lengthened by this difference in propagation delay.
Automatic test equipment (ATE) is often used to test and debug critical speed paths on newly designed microprocessors. The ATE is connected to the microprocessor to control a clock shrink circuit, which generates a test clock used to drive one or more functional units contained therein. The functional units include, for example, the data path, input units, execution units, cache, output units, and the like. The clock shrink circuit uses a technique called “clock shrinking”, by which the frequency of a clock (or group of clocks) is changed dynamically during the execution of a microprocessor. The term “shrinking” is used to denote that the frequency of a clock cycle of interest is reduced relative to other clock cycles. Clock shrinking is a debug tool for testing newly designed microprocessors and other types of integrated circuits. By shrinking a single clock (and leaving the other clocks at a lower, passing frequency), a single critical path can be isolated in a test or diagnostic that contains many critical speed paths.
FIG. 1 illustrates a prior art, on-chip clock shrink circuit 10 for shifting the phase of a clock signal (CLOCK). The clock shrink circuit 10 includes two identical circuit portions, a rise mirror circuit 12 and a fall mirror circuit 14. Each mirror circuit 12 and 14 includes the same components, with the mirror circuit 12 having a front end inverter 16 with an output signal CLOCKB, an inverting variable pull-up delay stage 18 and an inverting output stage 20 with an output signal CLOCKMID. The fall mirror circuit 14 is shown with an output signal CLOCKOUT.
Referring to FIG. 2, the operation of the clock shrink circuit 10 of the prior art is shown for an illustrative regular frequency (generally below 4 GHz) by showing in a timing diagram of the signals CLOCK, CLOCKB, CLOCKMID, and CLOCKOUT. The signal CLOCKB is an inverted, delayed version of the CLOCK signal, but retains the 50% duty cycle. The delay stage 18 of the rise mirror circuit 12 creates significantly different rise and fall propagation delays as illustrated by the CLOCKMID signal, with the rising input to falling output being much larger than the falling input to rising output. As such, the output duty cycle is significantly different than the input duty cycle, e.g., 50% input duty cycle results in a greater than 70% duty cycle output. In other words, the CLOCKMID waveform is more high than low during this regular frequency operation. With the assistance of the fall mirror circuit 14, the CLOCKOUT signal is the desired delayed clock signal with a 50% duty cycle.
Referring to FIG. 3, the operation of the clock shrink circuit 10 is shown for a high frequency (generally above 4 GHz) by again showing in a timing diagram the signals CLOCK, CLOCKB, CLOCKMID, and CLOCKOUT. As the clock frequency is increased, eventually the shrink circuit 10 becomes a frequency limiter. The CLOCKOUT signal no longer toggles in the high frequency operation.
Although the shrink circuit 10 is generally acceptable for frequencies approximately under 4 GHz, the clock shrink circuit 10 has insufficient bandwidth of operation as a serial circuit in the clock distribution path having frequencies approximately greater than 4 GHz. Currently, the maximum frequency of operation of the shrink circuit 10 is close to the nominal part frequency. This limits the maximum device frequency as the part speed is increased by fixing paths in the design.